1.Verilog HDL information at xxx.v:always construct contains both blocking and non-blocking assignments
在一個(gè)always塊中同時(shí)使用了阻塞和非阻塞賦值。

2.Warning: Parallel compilation is not licensed and has been disabled
并行編譯未獲得許可，已經(jīng)終止。

3.Warning (10227): Verilog HDL Port Declaration warning at v_led.v(4): data type declaration for "out" declares packed dimensions but the port declaration declaration does not
應(yīng)該在聲明引腳輸入輸出時(shí)就寫(xiě)明位寬，否在之后聲明就會(huì)出現(xiàn)以上錯(cuò)誤。如output out；reg[7:0] out；就會(huì)報(bào)警告，應(yīng)該寫(xiě)成output reg[7:0] out;才正確。

4.Warning (10230): Verilog HDL assignment warning at v_led.v(13): truncated value with size 32 to match size of target (8)
原因:在HDL設(shè)計(jì)中對(duì)目標(biāo)的位數(shù)進(jìn)行了設(shè)定,如:reg[4:0] a;而默認(rèn)為32位,將位數(shù)裁定到合適的大小
措施:如果結(jié)果正確,無(wú)須加以修正,如果不想看到這個(gè)警告,可以改變?cè)O(shè)定的位數(shù)

5.Warning: Found 9 output pins without output pin load capacitance assignment
 輸出引腳沒(méi)用輸出引腳負(fù)載電容。

6.Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
警告：保留所有未使用引腳的設(shè)置還沒(méi)有被指定，并且將默認(rèn)“作為驅(qū)動(dòng)輸出的‘地’”。

7.Warning: Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER
警告：跳過(guò)模塊“PowerPlay功耗分析儀”，由于分配FLOW_ENABLE_POWER_ANALYZER

8.Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
這個(gè)是比較詭異的警告，在網(wǎng)上搜了半天，沒(méi)有確切的解決辦法，這個(gè)信息大致的意思是未定義管腳設(shè)置接地，其實(shí)無(wú)關(guān)緊要，但是放在那不管很影響我的0warning記錄，于是在setting里面找，后來(lái)發(fā)現(xiàn)在device里有個(gè)對(duì)話框device and pin options，打開(kāi)后里面有個(gè)unused pins，把里面的選項(xiàng)由原來(lái)的接地改成三態(tài)，再仿真警告就沒(méi)了，但奇怪的是，后來(lái)我又改了回來(lái)，再仿真，警告還是沒(méi)有出現(xiàn)，不知何故。

9.Warning: Expected ENABLE_CLOCK_LATENCY to be set to ON but is set to OFF
這個(gè)是說(shuō)時(shí)鐘延遲的一個(gè)設(shè)置應(yīng)該設(shè)置為ON，網(wǎng)上都說(shuō)沒(méi)什么影響，貌似與時(shí)序仿真有關(guān)，不太清楚，設(shè)置在Classic Timing Analyzer中有個(gè)more setting，里面下拉菜單中就有ENABLE_CLOCK_LATENCY，設(shè)置為ON就OK。
PS：?jiǎn)栴}

How do I run the PowerPlay Power Analyzer automatically during compilation?
解決方案

In the Quartus? II software, you can enable the PowerPlay Power Analyzer to run automatically during compilation by adding the following assignment to your Quartus II Settings File (.qsf):

set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
This assignment is scheduled to be available in the Settings dialog box in a future release of the Quartus II software.

10.在Nios II中編譯時(shí)有如下提示warning: no newline at end of file
在最后的一個(gè)大括號(hào)外再加一個(gè)回車(chē)。